Efficient DFE Architecture for MIMO Communication Systems

We present a novel VLSI architecture of Multiple-input, multiple-output (MIMO) decision feedback equalization (DFE) which is based on the reduced complexity FIR filter structure. Compared with the SISO counterpart, a MIMO DFE has a formidable computation complexity. By applying the reduced complexity FIR filter techniques that reduce the use of multipliers at the expense of some additional switches, at least a 25% reduction in multipliers can be achieved. A 2 × 2 MIMO DFE design example is given. Complexity comparisons based on the implementations on Xilinx Virtex-4 are also discussed where a 20% reduction in slices used is reported.